The structure and functionality of non-volatile random access semiconductor memory devices has evolved in the last decade in order to match the specific needs and requirements of data storage and processing. Non-volatile memory devices are useful in many applications whenever data must be retained after devices are. powered off. Upon restart of many computing or entertainment devices, initialization data must be available to enable a processor to load its programs and operating systems from peripheral storage such as hard disks or optical compact disks. Desirable features of non-volatile semiconductor memory devices include large capacity, high speed of writing, high speed of readout, repeated erasability, ease of writing and erasing of data as well as specific practical features that may allow for example reading or writing to specific sectors within the memory while protecting other sectors.
An early example of erasable non volatile memory is the Erasable Programmable Read Only Memory or EPROM. EPROM devices comprise a multiplicity of memory cells generally arranged in arrays of several thousand cells on the surface of a semiconductor chip, each cell comprising one or more metal oxide semiconductor (MOS) transistors. Each MOS transistor has a first control gate that consists of a metallic area separated from the drain or depletion area of the transistor by a thin oxide film and a second electrically insulated gate located between the control gate and the drain. Such cells retain the data in the form of stored electrical charge on the insulated gate. In order to erase an EPROM electrons generated by ultraviolet radiation from a special erase lamp are utilized. Such devices necessarily require the erasing of all sectors of the memory followed by a re-write of the new data to all sectors of the memory. The rewrite operation consists of injecting hot electrons into the floating gate. Such write-erase processes can be time consuming and subject to error generation especially if only small sections of the data stored need to be modified. An EPROM generally requires a high-voltage supply with substantial current-generating capability to generate the hot electrons. Furthermore, the process of generating hot electrons degrades the transistor gate regions, which limits the number of erase-write cycles that can be performed.
A more recent type of memory device, called EEPROM or electrically erasable PROM, utilizes tunneling electrons generated by the application of a high voltage difference between a control gate located above the insulated gate and the drain region of the MOS transistor, to pump charge into or out of the insulated gate. An EEPROM is distinguished from an EPROM by two features:
1) the program and erase operations can be accomplished on a byte-by-byte basis, whereas, in an EPROM, the erase operation is global and only the program operation is byte-by-byte; and PA1 2) the mechanism underlying the program and erase operations in an EEPROM is Fowler-Nordheim (FN) tunneling, whereas, in an EPROM, it is hot-electron injection for programming (typically a high-current mechanism), and UV-erase for the erase operation.
Flash EPROMs, which have become the standard non-volatile memory are hybrid devices, share features of the EPROM and EEPROMS. That is, similarly to EPROMS, flash memories have a global (or sector, in more recent types) erase mode. Similarly to EEPROMS, flash memories can be erased and programmed electrically. The characteristics of the different types of non-volatile memory are summarized in Table 1. The present invention is implemented in a flash EPROM with tunneling program and sector tunneling erase. The basic operation of a Fowler-Nordheim flash EPROM is now described in reference to FIG. 1.
TABLE 1 ______________________________________ Memory Type Program Mechanism Erase Mechanism ______________________________________ EPROM hot-electron (high current) global (non-byte) UV EEPROM FN-tunneling (low current) FN-tunneling (byte operation) electrical Flash hot-electron or tunneling FN-tunneling global or semi- EPROM injection global (non-byte) electrical operation ______________________________________
Referring to FIG. 1, there is shown a block diagram of a flash memory 110. This block diagram is also representative of the architecture of other types of memories. The flash memory 110 includes a memory array 112, an address decoder 114, a control circuit 116, an input/output (I/O) data circuit 118 and a column I/O circuitry 120. The memory 110 operates in response to external signals provided by a controlling device 122, such as a microprocessor.
The principle of operation of flash memories, such as the memory 110, is well known and therefore is only briefly described herein. The controller 122 initiates a memory operation by asserting a chip enable signal 101 and supplying address signals A0-AN (corresponding to 2N+1 memory locations) designating the address of a memory location where the operation is to be performed. If the memory operation is a write operation, the controller 122 supplies the data to be written to the addressed memory location via the bidirectional input output lines I/O0-I/Ok (corresponding to k+1 bit memory words). If the memory operation is a read operation, the stored information from the addressed location is read out from the same bidirectional input output lines I/O0-I/Ok. The memory 110 also provides connections for external power supply (Vcc) and ground (GND) signals.
The heart of the memory 110 is the memory array 112, which consists of flash memory cells, each capable of storing one bit of data, arranged in rows and columns. In the conventional manner, all of the cells in one row are energized for a memory operation (either a read or a write) by a word line WL uniquely associated with that row. A memory operation cannot be performed unless the word line associated with the target row of cells is activated.
At least a subset of the cells in a row (typically all of the cells that store data for one memory word) can be accessed simultaneously for a given memory operation via the bit lines BL. When the memory operation is a read, the bit lines BL are coupled to sense amplifiers in the column I/O 120 that "sense" the data stored in the corresponding cells of the row whose word line WL is active. When the memory operation is a write operation the bit lines BL carry the signals used to program the corresponding cells of the row associated with the active word line.
The control circuitry 116 controls the other blocks of the memory 110 in accordance with the chip enables 101. Depending on the operation to be performed, the control circuitry issues the appropriate control signals 117a, 117b to the decoder 114 and the I/O data circuit, respectively.
Regardless of whether the memory operation is a write or a read, the decoder 114 decodes the address signals A0-AN and activates the word line WL of the row that includes the memory word that is the target of the current memory operation. If the operation is a write, the I/O data circuitry 118 buffers the input data signals I/O0-I/Ok and outputs the buffered data to the column I/O 120 via the bidirectional data bus 119. The column I/O 120 then latches the input signals in parallel onto the corresponding bit lines BL-BLK The signals on the bit lines BL0-BLK are used to program the cells composing the word whose word line was activated for the current operation by the decoder 114.
If the operation is a read, sense amplifiers in the column I/O 120 sense the signals on the respective bit lines BL, convert the sensed signals into binary (e.g., high or low) voltages that represent the programmed state of the addressed word and output the word's bit values to the I/O data circuit via the bi-directional bus 119. The output data are buffered by the I/O data circuit 118 and latched onto the bi-directional data lines I/O0-I/Ok for use by the controller 122.
The operation so far described is typical of most memories. For the sake of clarity the physical writing process is now more specifically described in reference to Table 2.
Table 2 shows the voltages applied to the gate (Vg), drain (Vd), source (Vs) and bulk (Vb) of a MOS transistor constituting a storage cell for read, write and erase operations. In the write and erase modes, the indicated voltages affect the cell's threshold voltage Vt as shown (e.g., low or high), where Vt is defined as the voltage that must be applied across the gate and source of a storage cell to make it conduct during a sense or read operation. In the preferred embodiment, the voltages Vpp, Vpn and Vcc are 10V, -10 V and 3.0 V, respectively. As for other terms used in Table 2, "floating" means the voltage is allowed to take on any value under the applied conditions and Vcc+ is a voltage larger than Vcc.
TABLE 2 ______________________________________ Vg Vd Vs Vb Vt ______________________________________ READ Vcc 1-1.2 V 0 V 0 V unchanged WRITE Vpn Vcc+ floating 0 low ERASE Vpp floating Vpn Vpn high ______________________________________
In a write operation the high negative voltage Vpn applied to a cell's control gate encourages positive charges to tunnel to the cell's insulated gate. This decreases the cell's Vt (hence the low Vt) because the stored positive charge supplements the gate voltage applied during a subsequent read operation performed on that cell.
Conversely, in an erase operation the high positive voltage Vpp applied to a cell's control gate encourages negative charges to tunnel to the cell's insulated gate. This increases the cell's Vt (hence the low Vt) because the stored negative charge counteracts the gate voltage applied during a subsequent read operation performed on that cell.
Because of manufacturing-induced variations between cells, applying the voltages prescribed in Table 2 during a write operation results in different values of Vt for different cells. As a consequence the required voltage Vt to sense the data stored in a particular cell will vary from cell to cell. Such variations must be contained within acceptable limits in order to assure the proper operation of the storage device, especially in cases where a low Vcc circuit is used. For example, if Vcc=2.5 V and the variance in Vt is 0.6 volts (possibly resulting in a Vt that is higher than the Vcc level coupled to the gate during a read operation) it is not possible to achieve reliable operation of the memory device. Therefore, it is imperative to verify that the Vt of all of the written cells is within an optimal range for the operating environment.
A general verification method employed in the prior art is to repeat the writing process several times to ensure that the Vt is low enough. This repeated writing is applied to all cells regardless of whether the Vt is already low enough after the first write. Such repeated writing stresses the oxide layer that constitutes the insulation between the gate and bulk and shortens the useful life of the storage device. Another disadvantage of the prior art is that over-writing a cell lowers Vt to such a low value that current leakage starts occurring between the cell's source and drain even when there is no memory activity. When leakage occurs a healing step must be further applied to bring back Vt to an acceptable level. Such a healing step requires additional circuitry and adds complexity to the writing process.
Accordingly, several objectives the present invention include: providing a method of achieving a controllable Vt at each storage cell, preventing over-stressing of the oxide insulating layer and allowing the active verification of the written data while simultaneously loading new data.